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From data centre accelerators to low-power embedded devices, QBayLogic delivers right the first time FPGA solutions for every design challenge.
Our team has a strong affinity for both mathematics and embedded systems, which allows us to quickly achieve a deep understanding of difficult algorithms and to find suitable implementations. We deliver FPGA accelerators on time and meet the most stringent performance requirements, as a result our unique design methodology.
We achieve these results by developing both the algorithms and the FPGA architecture in the functional programming language called Haskell. Using Haskell we create executable specifications of the algorithm enabling us to effectively communicate with your domain experts, quickly iterating towards the desired behavior.
Using our Haskell-to-Verilog compiler, called Clash, we can then derive the FPGA architecture in the same language, ensuring that the behavior of algorithms and the behavior of the FPGA implementation remain in-sync, enabling a truly model-based design flow.
Even though Haskell is a high-level programming language, the Clash compiler is set up in such a way that a designer remains in full control of the Quality of Results. We use modern software engineering practices to continuously test our designs ensuring that we deliver a correctly working product on time.
Because we want everyone in the industry, but especially our clients, to benefit from our advances in FPGA design we also provide training and workshops in our methodology and distribute our tools for free under the permissive BSD license.
Tel: +31 (0)85 8000 380